*****************************************
Testing: addtest.s
* Compiling memory image...
SPIM Version 6.2 of January 11, 1999
Copyright 1990-1998 by James R. Larus (larus@cs.wisc.edu).
All Rights Reserved.
See the file README for a full copyright notice.
Loaded: /afs/ece.cmu.edu/class/ece347/bin/trap.handler
* Running modelsim...
Reading /afs/ece.cmu.edu/support/mgc/share/image/usr/local/mgc/modelsim/5.7a/tcl/vsim/pref.tcl 
Reading /afs/ece/usr/cst/modelsim.tcl 

# 5.7a

# vsim -do {run -all; exit} -keepstdout -c -quiet testjig 
# //  ModelSim SE VLOG 5.7a Dec 15 2002 SunOS 5.8
# //
# //  Copyright Model Technology, a Mentor Graphics Corporation company, 2003
# //                         All Rights Reserved.
# //                   UNPUBLISHED, LICENSED SOFTWARE.
# //         CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //        PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
# run -all; exit 
# [End of program at 0x00400070]
# R          0 = 00000000
# R          1 = 00000000
# R          2 = 0000000a
# R          3 = 00000000
# R          4 = 000000ff
# R          5 = 000000ff
# R          6 = 000001fe
# R          7 = 000003fc
# R          8 = 00000000
# R          9 = 00000000
# R         10 = 00000000
# R         11 = 00000000
# R         12 = 00000000
# R         13 = 00000000
# R         14 = 00000000
# R         15 = 00000000
# R         16 = 00000000
# R         17 = 00000000
# R         18 = 00000000
# R         19 = 00000000
# R         20 = 00000000
# R         21 = 00000000
# R         22 = 00000000
# R         23 = 00000000
# R         24 = 00000000
# R         25 = 00000000
# R         26 = 00000000
# R         27 = 00000000
# R         28 = 00000000
# R         29 = 7fffeffc
# R         30 = 10008000
# R         31 = 0040001c
# Break at testjig_core.v line 81
# Stopped at testjig_core.v line 81 

TA comments:
hooray for you

Score: 5/5

*****************************************
Testing: arithtest.s
* Compiling memory image...
SPIM Version 6.2 of January 11, 1999
Copyright 1990-1998 by James R. Larus (larus@cs.wisc.edu).
All Rights Reserved.
See the file README for a full copyright notice.
Loaded: /afs/ece.cmu.edu/class/ece347/bin/trap.handler
* Running modelsim...
Reading /afs/ece.cmu.edu/support/mgc/share/image/usr/local/mgc/modelsim/5.7a/tcl/vsim/pref.tcl 
Reading /afs/ece/usr/cst/modelsim.tcl 

# 5.7a

# vsim -do {run -all; exit} -keepstdout -c -quiet testjig 
# //  ModelSim SE VLOG 5.7a Dec 15 2002 SunOS 5.8
# //
# //  Copyright Model Technology, a Mentor Graphics Corporation company, 2003
# //                         All Rights Reserved.
# //                   UNPUBLISHED, LICENSED SOFTWARE.
# //         CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //        PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
# run -all; exit 
# ** Error: dreg.v(27): $hold( posedge clk:27500 ns, dCheck:27500 ns, 1 ns );
#    Time: 27500 ns  Iteration: 8  Instance: /testjig/core/hiLo[0]/dFF
# ** Error: dreg.v(27): $hold( posedge clk:27500 ns, dCheck:27500 ns, 1 ns );
#    Time: 27500 ns  Iteration: 8  Instance: /testjig/core/hiLo[1]/dFF
# ** Error: dreg.v(27): $hold( posedge clk:28500 ns, dCheck:28500 ns, 1 ns );
#    Time: 28500 ns  Iteration: 8  Instance: /testjig/core/hiLo[0]/dFF
# ** Error: dreg.v(27): $hold( posedge clk:28500 ns, dCheck:28500 ns, 1 ns );
#    Time: 28500 ns  Iteration: 8  Instance: /testjig/core/hiLo[1]/dFF
# ** Error: dreg.v(27): $hold( posedge clk:32500 ns, dCheck:32500 ns, 1 ns );
#    Time: 32500 ns  Iteration: 8  Instance: /testjig/core/hiLo[0]/dFF
# ** Error: dreg.v(27): $hold( posedge clk:32500 ns, dCheck:32500 ns, 1 ns );
#    Time: 32500 ns  Iteration: 8  Instance: /testjig/core/hiLo[1]/dFF
# ** Error: dreg.v(27): $hold( posedge clk:33500 ns, dCheck:33500 ns, 1 ns );
#    Time: 33500 ns  Iteration: 8  Instance: /testjig/core/hiLo[0]/dFF
# ** Error: dreg.v(27): $hold( posedge clk:33500 ns, dCheck:33500 ns, 1 ns );
#    Time: 33500 ns  Iteration: 8  Instance: /testjig/core/hiLo[1]/dFF
# [End of program at 0x004000d8]
# R          0 = 00000000
# R          1 = 00000000
# R          2 = 0000000a
# R          3 = 00000800
# R          4 = 00000c00
# R          5 = 000004cf
# R          6 = 04cf0000
# R          7 = 04cf270f
# R          8 = 04cf230f
# R          9 = 00000400
# R         10 = 000004ff
# R         11 = 00267800
# R         12 = 004cf000
# R         13 = 00000000
# R         14 = 00000000
# R         15 = fffffb01
# R         16 = 000004fe
# R         17 = 00640000
# R         18 = 00000000
# R         19 = 00000001
# R         20 = 00000000
# R         21 = 00000001
# R         22 = ffffffec
# R         23 = c363c400
# R         24 = 0000017b
# R         25 = 0000f66c
# R         26 = 00000000
# R         27 = 00000000
# R         28 = 00000000
# R         29 = 7fffeffc
# R         30 = 10008000
# R         31 = 0040001c
# Break at testjig_core.v line 81
# Stopped at testjig_core.v line 81 

TA comments: