ncverilog: v03.11.(s020): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
Loading snapshot worklib.NAND2:v .................... Done
ncsim> source /usr/cds/ldv-3.1/tools/inca/files/ncsimrc
ncsim> run
InstructionMemory: Starting execution at instruction address 0
InstructionMemory: Execution ending at instruction address         30
STOP: END OF PROGRAM
Dumping register state: 
R          0: 0x00000000 (          0 )
R          1: 0x00000000 (          0 )
R          2: 0x000003ff (       1023 )
R          3: 0x00000400 (       1024 )
R          4: 0x00003fff (      16383 )
R          5: 0x00004400 (      17408 )
R          6: 0x00000001 (          1 )
R          7: 0xffffffff ( 4294967295 )
R          8: 0x00000400 (       1024 )
R          9: 0xff000000 ( 4278190080 )
R         10: 0xffffc000 ( 4294950912 )
R         11: 0x003fc000 (    4177920 )
R         12: 0xffc00000 ( 4290772992 )
R         13: 0xff800000 ( 4286578688 )
R         14: 0x0000000f (         15 )
R         15: 0x00008fff (      36863 )
R         16: 0x0f0f0f00 (  252645120 )
R         17: 0x1e1e1e0f (  505290255 )
R         18: 0x1e1e1e0f (  505290255 )
R         19: 0xf0f180ff ( 4042359039 )
R         20: 0x00011ffe (      73726 )
R         21: 0x1e1f3e0d (  505363981 )
R         22: 0x000007fe (       2046 )
R         23: 0x00000000 (          0 )
R         24: 0x00000000 (          0 )
R         25: 0x00000000 (          0 )
R         26: 0x00000000 (          0 )
R         27: 0x00000000 (          0 )
R         28: 0x00000000 (          0 )
R         29: 0x00000000 (          0 )
R         30: 0x00000000 (          0 )
R         31: 0x00000000 (          0 )
Done.  Simulation ending.
Simulation complete via $finish(1) at time 30500 NS + 33
./lab2_template.v:205              $finish;
ncsim> exit