ncverilog: v03.11.(s020): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
file: lab2_template.v
	module worklib.AND2:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.NAND2:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.AND3:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.NAND3:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.AND4:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.NAND4:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.OR2:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.NOR2:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.OR3:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.NOR3:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.OR4:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.NOR4:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.XOR2:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.XNOR2:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.NOT:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.BUF:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.decoder:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.mux4:v
		errors: 0, warnings: 0
	module worklib.alu:v
		errors: 0, warnings: 0
	module worklib.rom:v
		errors: 0, warnings: 0
	module worklib.InstructionMemory:v
		errors: 0, warnings: 0
	module worklib.regfile_3port:v
		errors: 0, warnings: 0
	module worklib.dff_rse:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.dff_re:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.dff_r:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.Clock:v (up-to-date)
		errors: 0, warnings: 0
	module worklib.MiniComputer:v
		errors: 0, warnings: 0
	module worklib.foo:v (up-to-date)
		errors: 0, warnings: 0
		Caching library 'worklib' ....... Done
	Elaborating the design hierarchy:
	Building instance overlay tables: .
        $readmemb ( "memory.dat", memWords );
                                         |
ncelab: *W,MEMODR (./lab2_template.v,76|41): $readmem default memory order incompatibile with IEEE1364.
................... Done
	Generating native compiled code:
		worklib.InstructionMemory:v <0x3aa6bdbb>
			streams:   3, words:   297
		worklib.MiniComputer:v <0x109b3854>
			streams:   0, words:     0
		worklib.alu:v <0x204ee74b>
			streams:  11, words:   961
		worklib.decoder:v <0x2c63102b>
			streams:   2, words:  2383
		worklib.regfile_3port:v <0x4663107d>
			streams:   4, words:   884
		worklib.rom:v <0x6678e2d0>
			streams:   2, words:   214
	Loading native compiled code:     .................... Done
	Building instance specific data structures.
	Design hierarchy summary:
		                Instances  Unique
		Modules:              345      28
		Primitives:           304       8
		Registers:             59      29
		Scalar wires:          44       -
		Expanded wires:      1153      37
		Vectored wires:        24       -
		Always blocks:         70      10
		Initial blocks:         4       4
		Cont. assignments:     12      20
		Pseudo assignments:     4       4
	Writing initial simulation snapshot: worklib.NAND2:v
Loading snapshot worklib.NAND2:v .................... Done
ncsim> source /usr/cds/ldv-3.1/tools/inca/files/ncsimrc
ncsim> run
InstructionMemory: Starting execution at instruction address 0
STOP: EXECUTION HALTED DUE TO OVERFLOW
Dumping register state: 
R          0: 0x00000000 (          0 )
R          1: 0x00000000 (          0 )
R          2: 0x000003ff (       1023 )
R          3: 0x00000400 (       1024 )
R          4: 0x00003fff (      16383 )
R          5: 0x00004400 (      17408 )
R          6: 0x00010000 (      65536 )
R          7: 0xffffffff ( 4294967295 )
R          8: 0x00000400 (       1024 )
R          9: 0xff000000 ( 4278190080 )
R         10: 0xffffc000 ( 4294950912 )
R         11: 0x003fc000 (    4177920 )
R         12: 0xffc00000 ( 4290772992 )
R         13: 0xff800000 ( 4286578688 )
R         14: 0x00000000 (          0 )
R         15: 0x00000000 (          0 )
R         16: 0x00000000 (          0 )
R         17: 0x00000000 (          0 )
R         18: 0x00000000 (          0 )
R         19: 0x00000000 (          0 )
R         20: 0x00000000 (          0 )
R         21: 0x00000000 (          0 )
R         22: 0x00000000 (          0 )
R         23: 0x00000000 (          0 )
R         24: 0x00000000 (          0 )
R         25: 0x00000000 (          0 )
R         26: 0x00000000 (          0 )
R         27: 0x00000000 (          0 )
R         28: 0x00000000 (          0 )
R         29: 0x00000000 (          0 )
R         30: 0x00000000 (          0 )
R         31: 0x00000000 (          0 )
Done.  Simulation ending.
Simulation complete via $finish(1) at time 13500 NS + 33
./lab2_template.v:205              $finish;
ncsim> exit